bug 14192 fix + 0 divide bug fix 21/18221/2
authorSerge Steer <serge.steer@scilab.org>
Mon, 6 Jun 2016 13:53:14 +0000 (15:53 +0200)
committerClément DAVID <clement.david@scilab-enterprises.com>
Thu, 23 Jun 2016 08:02:32 +0000 (10:02 +0200)
commit8af6f4b7c1440354dca07d33590fba038ee5efd3
tree884dbf168ed3be9a3b75a2aa38169a7280a1ccac
parent5b423599a9d5c073fa90db3e48b667ca59bb6a7c
bug 14192 fix + 0 divide bug fix

Change-Id: I88adc7886c573f6ccf29653b3460999061580c93
scilab/CHANGES.md
scilab/modules/cacsd/macros/g_margin.sci
scilab/modules/cacsd/tests/nonreg_tests/bug_14192.dia.ref [new file with mode: 0644]
scilab/modules/cacsd/tests/nonreg_tests/bug_14192.tst [new file with mode: 0644]