syredi.tst changed in signal processing module. 31/18831/2
Adeline CARNIS [Tue, 3 Jan 2017 10:32:03 +0000 (11:32 +0100)]
Change-Id: I66f47be6e918031fe48097ff2db75b0f7ebfd648

scilab/modules/signal_processing/tests/unit_tests/syredi.dia.ref
scilab/modules/signal_processing/tests/unit_tests/syredi.tst

index 606fb9c..c3d07b4 100644 (file)
@@ -26,11 +26,11 @@ load(test_path+"syredi.h5");
 [fact1, b21, b11, b01, c11, c01, zzeros1, zpoles1] = syredi(1, 4, [1, 2, 0, 0], 0.02, 0.001);
 assert_checkequal(fact1, fact1_ref);
 assert_checkequal(b21, b21_ref);
-assert_checkequal(b11, b11_ref);
+assert_checkalmostequal(b11, b11_ref);
 assert_checkequal(b01, b01_ref);
 assert_checkalmostequal(c11, c11_ref);
 assert_checkalmostequal(c01, c01_ref, [], %eps);
-assert_checkequal(zzeros1, zzeros1_ref);
+assert_checkalmostequal(zzeros1, zzeros1_ref);
 assert_checkalmostequal(zpoles1, zpoles1_ref);
 [fact2, b22, b12, b02, c12, c02, zzeros2, zpoles2] = syredi(3, 4, [1, 2, 3, 3.01], 0.1, 0.001);
 assert_checkalmostequal(fact2, fact2_ref);
index ed4ed5c..149f1e6 100644 (file)
@@ -29,11 +29,11 @@ load(test_path+"syredi.h5");
 [fact1, b21, b11, b01, c11, c01, zzeros1, zpoles1] = syredi(1, 4, [1, 2, 0, 0], 0.02, 0.001);
 assert_checkequal(fact1, fact1_ref);
 assert_checkequal(b21, b21_ref);
-assert_checkequal(b11, b11_ref);
+assert_checkalmostequal(b11, b11_ref);
 assert_checkequal(b01, b01_ref);
 assert_checkalmostequal(c11, c11_ref);
 assert_checkalmostequal(c01, c01_ref, [], %eps);
-assert_checkequal(zzeros1, zzeros1_ref);
+assert_checkalmostequal(zzeros1, zzeros1_ref);
 assert_checkalmostequal(zpoles1, zpoles1_ref);
 
 [fact2, b22, b12, b02, c12, c02, zzeros2, zpoles2] = syredi(3, 4, [1, 2, 3, 3.01], 0.1, 0.001);