Changes between version 5.4.0-beta-2 and 5.4.0-beta-3 of Scilab
===============================================================
+Xcos
+====
+
+* Bug #10781 fixed - DFlipflop incorrectly reported problem in port size or type
+
Obsolete functions
==================
sz=[40,40],..
flip=%t,..
theta=0,..
- exprs="1",..
+ exprs="5",..
pin=5,..
pout=33,..
pein=42,..
in=[model.in model.in2];
[model,graphics,ok]=set_io(model,graphics,list(in,it),list(in,it),1,[])
if ok then
- graphics.exprs=label;
+ graphics.exprs=exprs;
arg1.graphics=graphics;arg1.model=model;
x=arg1
break
--- /dev/null
+// =============================================================================
+// Scilab ( http://www.scilab.org/ ) - This file is part of Scilab
+// Copyright (C) 2012 - DIGITEO - Alexandre HERISSE
+//
+// This file is distributed under the same license as the Scilab package.
+// =============================================================================
+// <-- TEST WITH XCOS -->
+//
+// <-- Non-regression test for bug 10781 -->
+//
+// <-- Bugzilla URL -->
+// http://bugzilla.scilab.org/show_bug.cgi?id=10781
+//
+// <-- Short Description -->
+// DFlipflop should not report problem in port size or type
+assert_checktrue(importXcosDiagram(SCI + "/modules/xcos/tests/nonreg_tests/bug_10781.xcos"));
+// compile and simulate
+xcos_simulate(scs_m, 4);
+lastQ=double(Q.values($));
+lastnonQ=double(nonQ.values($));
+assert_checkequal(lastQ, 1);
+assert_checkequal(lastnonQ, 0);
--- /dev/null
+// =============================================================================
+// Scilab ( http://www.scilab.org/ ) - This file is part of Scilab
+// Copyright (C) 2012 - DIGITEO - Alexandre HERISSE
+//
+// This file is distributed under the same license as the Scilab package.
+// =============================================================================
+
+// <-- TEST WITH XCOS -->
+//
+// <-- Non-regression test for bug 10781 -->
+//
+// <-- Bugzilla URL -->
+// http://bugzilla.scilab.org/show_bug.cgi?id=10781
+//
+// <-- Short Description -->
+// DFlipflop should not report problem in port size or type
+
+assert_checktrue(importXcosDiagram(SCI + "/modules/xcos/tests/nonreg_tests/bug_10781.xcos"));
+
+// compile and simulate
+xcos_simulate(scs_m, 4);
+
+lastQ=double(Q.values($));
+lastnonQ=double(nonQ.values($));
+
+assert_checkequal(lastQ, 1);
+assert_checkequal(lastnonQ, 0);